The design of very large-scale integrated (VLSI) circuits using computer aided design (CAD) systems is a very time consuming and computationally intensive process. As the complexity of VLSI circuit design has increased, circuit designers have begun incorporating basic circuit building blocks into circuit designs so that the designers do not need to start from scratch for each design. This design approach is commonly referred to as an intellectual property (IP) based design approach and the basic circuit building blocks are referred to as IP blocks.
In accordance with system on chip (SOC) technology, a variety of circuit building blocks are incorporated onto a single integrated chip. Each of the building blocks performs a specific function of an electronic system. The IP building blocks include, but are not limited to, embedded memory, standard cell, I/O devices, analog and system interfaces, etc. . . .
A timing model including many characterized timing parameters for each IP block that is to be incorporated into a system chip is required by the IC designers. Important timing parameters include setup time, hold time, access time, minimum pulse high and low time, and other I/O pin characteristics. Designers are interested in characterizing and optimizing timing characteristics associated with an IP block design.
There are two methods of IP block characterization and verification. The first method is based on ‘full circuit’ simulations. For deep submicron designs, a netlist size of layout-extracted IP blocks could be enormous with a large number of resistors and capacitors. It might be prohibitive to run numerous full circuit simulations with a high-accuracy circuit simulator. The other method is a characterization based on ‘critical-path circuit’ simulations. Instead of using a full circuit, a small detailed critical circuit including multiple critical paths is used of simulation. The ‘critical-path circuits’ are built either manually or by software tools for automation, accuracy and performance.
The simulation results observed during the characterization process are only at the pins of the full circuit or at ports of the ‘critical-path circuit’. Reliability issues such as noise margin, glitch, and racing conditions that occur inside the circuit are normally ignored. Accordingly, the timing parameters generated by the simulation may be too optimistic and incorrect.
Furthermore, the circuit or subcircuit block is viewed as a black-box when the circuit simulation is performed. However, the simulations results observed at the pins cannot detect the above-mentioned reliability issues that can occur inside the circuit. The models based upon simulation and characterization results could be incorrect thereby causing yield and reliability problems.